Synchronous Dynamic RAMs (SDRAMs) have become a popular type of dynamic memory due to their speed of operation and ease of use. SDRAMs are used in motherboards, embedded products such as RAID controllers, routers, Ethernet controllers and other systems that employ memory. Some of these products, such as RAID controllers, cannot afford to have their memory data corrupted upon the occurrence of resets. A reset can either be a cold reset, which is initiated by a power-on event, or a warm reset, which is initiated by software or a user from a panel switch.
Most external SDRAM memory controllers do not protect data stored in the memory from corruption during warm resets. A SDRAM memory controller that provides such protection is able to be reset internally while preventing data corruption of the SDRAMs it supports. In one prior art system reset hardware is used to detect a warm system reset. The hardware then triggers auto-refresh circuitry to set the SDRAM to an auto-refresh mode in which auto refresh cycles are initiated periodically throughout the entire period during which the warm reset is held active. Each auto-refresh cycles refreshes the data in the SDRAM so as to prevent its corruption. A disadvantage of this method is that the SDRAM has to be periodically refreshed by the external hardware while in auto refresh mode. The reset valid time (i.e., the duration of a reset operation) could be on the order of milliseconds and, as a result, several auto refresh cycles could be required to keep intact the SDRAM data.
Therefore, it would be desirable to provide a system and method for protecting SDRAM data during warm resets that does not require extensive intervention from the reset hardware.